1. Field of the Invention
The invention relates generally to a circuit configuration and method of manufacture of a transient voltage suppressor (TVS). More particularly, this invention relates to an improved circuit configuration and method of manufacture with optimized configuration to integrate steering diodes for achieving a reduced capacitance for a transient voltage suppressor (TVS).
2. Description of the Relevant Art
The transient voltage suppressors (TVS) are commonly applied for protecting integrated circuits from damages due to the inadvertent occurrence of an over voltage imposed onto the integrated circuit. An integrated circuit is designed to operate over a normal range of voltages. However, in situations such as electrostatic discharge (ESD), electrical fast transients and lightning, an unexpected and an uncontrollable high voltage may accidentally strike onto the circuit. The TVS devices are required to serve the protection functions to circumvent the damages that are likely to occur to the integrated circuits when such over voltage conditions occur. As increasing number of devices are implemented with the integrated circuits that are vulnerable to over voltage damages, demands for TVS protection are also increased. Exemplary applications of TVS can be found in the USB power and data line protection, Digital video interface, high speed Ethernet, Notebook computers, monitors and flat panel displays.
FIG. 1A-1 shows a conventional TVS circuit implemented with diode array commonly applied for electrostatic discharge (ESD) protection of high bandwidth data buses. The TVS array includes a main Zener diode operated with two sets of steering diodes, i.e., the high side steering diode and the low side steering diode. The high side steering diode connects to the voltage source Vcc and the low side steering diode connects to the ground terminal GND with an input/output port connected between the high side and low side steering diodes. The Zener diode has a large size to function as an avalanche diode from the high voltage terminal, i.e., terminal Vcc, to the ground voltage terminal, i.e., terminal Gnd. At a time when a positive voltage strikes on one of the I/O (input/output) terminal, the high side diodes provide a forward bias and are clamped by the large Vcc-Gnd diodes, e.g., the Zener diode. The high side and low side steering diodes are designed with a small size to reduce the I/O capacitance and thereby reducing the insertion loss in high-speed lines such as fast Ethernet applications.
As an industry trend, the steering diodes are integrated with the Zener diodes. FIGS. 1A-2 and 1A-3 are two diagrams to show the integration of the steering diodes with the Zener diode. The high side and low side terminals are not visible from the outside. FIG. 1A-2 shows the integration of the high side steering diodes and low side steering diodes with a uni-directional Zener diode. To the outside, the diode unit looks like a Zener diode with very low capacitance, but internally high-side and low-side diodes are integrated with a Zener diode. The internal circuit is the same as the circuit in FIG. 1A-1. The I/O terminal is the cathode, and the GND terminal is the anode, and the VCC terminal may be internalized so that it is not noticed from the outside. FIG. 1A-3 shows the integration of the high side steering diodes and low side steering diodes with a bi-directional Zener diode circuit. However, for modern application to the electronic devices, the protection circuit implemented with such integration must be carried out without increasing the layout areas. Furthermore, there must have careful design optimization to obtain the best tradeoff between the capacitance and the forward biased voltage of the steering diodes in order to achieve a good overall voltage clamping.
FIG. 1B shows a standard circuit diagram for a conventional TVS circuit and FIG. 1B-1 is a cross sectional view for showing the actual implementation of the TVS circuit applying the CMOS processing technologies to provide the TVS circuit as integrated circuit (IC) chips. As shown in FIG. 1B-1, the device is manufactured using the CMOS processing technologies to produce diodes and NPN and PNP transistors in the semiconductor substrate with the diodes and the transistors extended along a lateral direction. The TVS circuits produced by implementing the device layout and configurations thus occupy greater areas on a substrate. It is therefore difficult to miniaturize the electronic device protected by TVS circuits as shown in FIG. 1B-1.
The inventor of this patent application disclosed a TVS circuit in a pending patent application U.S. Ser. No. 11/606,602 with new and improved device configuration shown in FIG. 1C. This application is a Continuation-in-Part (CIP) and claims the Priority of application Ser. No. 11/606,602. The disclosures made in patent application Ser. No. 11/606,602 are hereby incorporated by reference in this patent application. FIG. 1C shows a TVS circuit implemented with a main Zener diode formed in a P Body/N-Epi junction. The TVS circuit as shown in FIG. 1C has significant improvement by reducing the areas occupied by the device because the main Zener diode and high side diodes are now formed with a vertical configuration. This circuit uses two I/O terminals and two corresponding sets of high side and low side diodes but reversed the conductivity types of each region. The high side steering diodes is further insulated from the main Zener diode with isolation trenches thus prevent inadvertent turning on of the parasitic transistors along the lateral direction.
However, there are still further demand to reduce the areas occupied by the high side and low side steering diodes. Also, there are additional requirements to further reduce the capacitance of the steering diodes. Therefore, there are demands to provide new and improved device configurations with new structural layout and manufacturing method to achieve these goals. The new device configuration and method of manufacturing must also take into consideration a process of design optimization of the epitaxial layer with controlled doping concentration and epitaxial thickness to obtain the best tradeoff between the capacitance reduction and maintaining appropriate Zener breakdown voltage.
Therefore, a need still exists in the fields of circuit design and device manufactures for providing a new and improved circuit configuration and manufacturing method to resolve the above-discussed difficulties. Specifically, a need still exists to provide new and improved TVS circuits that can provide low cost high-density TVS circuits with reduced capacitance and good voltage clamping performance for portable electronic devices.